This invention relates to a semiconductor non-volatile memory and more particularly to a floating gate avalanche injection type metal-oxide-semiconductor memory with improved writing characteristics.
Metal-oxide-semiconductor (which is abbreviated to an "MOS") type semiconductor non-volatile memories are sorted into the floating gate avalanche injection MOS type memories having a floating gate in each memory cell and the metal nitride oxide semiconductor type memories having a gate insulating film with a double layer structure in each memory cell. Those two types of memories are abbreviated as "FAMOS" and "MNOS" respectively. In the FAMOS type, the memory cell has an operating mechanism by which a trap for accumulating electric charge is located in a band of the floating gate, while in the MNOS type the trap is located at a boundary level formed between a pair of electrically insulating films formed of dissimilar materials. The generation of hot carriers for storing information relies upon avalanche breakdown.
The semiconductor non-volatile memory of the type referred to forms a read only memory (which is abbreviated as "ROM") which is one of the elements included in microprocessors, microcomputers etc. A random access memory (which is abbreviated as "RAM") is used for writing and reading and is required to be operative at a higher speed and at a higher packing density. In order to attain the high speed operation, it is desirable to increase the conductance of the MOS transistors forming the selective gate unit of these memories. To this end, it is desirable to decrease both the threshold voltage V.sub.TH and the body effect constant K provided that the normalized size effect is considered.
On the other hand, an increase in degree of integration requires both a double layer structure of memory cells and a decrease in spacing between the source and drain regions in the MOS structure. To prevent a decrease in the punch-through voltage caused by this decrease in source-to-drain spacing then it is necessary to increase the impurity concentration of the semiconductor substrates. However, this increase in impurity concentration causes problems because both the body effect constant K, and the threshold voltage V.sub.TH described above increase to impede the high speed operation.
In order to solve those problems, there have been already proposed MOS type semiconductor non-volatile memories including a semiconductor substrate and a semiconductor region for each memory cell identical in conductivity type to the semiconductor substrate and higher in impurity concentration than the semiconductor substrate with a junction formed between that region and the drain region involved. In those MOS semiconductor non-volatile memories, the junction between the high impurity concentration region and the drain region extends outside of the associated gate region and therefore the writing avalanche breakdown current does not greatly contribute to the storing action as compared with memories not including the high impurity concentration region.
Accordingly, it is an object of the present invention to provide a new and improved semiconductor non-volatile memory capable of attaining both high speed operation and high packing density while efficiently storing data with a low writing voltage.